Leakage in Nanometer CMOS Technologies (Integrated Circuits by Siva G. Narendra, Anantha P. Chandrakasan

By Siva G. Narendra, Anantha P. Chandrakasan

Covers intimately promising strategies on the machine, circuit, and structure degrees of abstraction after first explaining the sensitivity of many of the MOS leakage assets to those stipulations from the 1st ideas. additionally handled are the ensuing results so the reader is aware the effectiveness of leakage strength relief ideas below those assorted stipulations. Case experiences offer real-world examples that benefit from leakage energy relief ideas because the booklet highlights varied equipment layout offerings that exist to mitigate raises within the leakage parts as know-how scales.

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Leakage in Nanometer CMOS Technologies (Integrated Circuits and Systems)

Covers intimately promising ideas on the equipment, circuit, and structure degrees of abstraction after first explaining the sensitivity of a number of the MOS leakage assets to those stipulations from the 1st rules. additionally handled are the ensuing results so the reader is aware the effectiveness of leakage energy relief recommendations less than those assorted stipulations.

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Leakage Dependence on Input Vector 31 to -100 mV. Thus, as shown in Figure 2-9, smaller amounts of leakage reduction are obtained at higher temperatures due to larger sub-threshold swing. For 3- or 4-transistor stacks, the leakage reduction is found to be 23X larger in both NMOS and PMOS, as illustrated in Figure 2-10. 12 J NMOS r ^^1^^ -• 9 c c 8 •2 7 J u PMOS High Vt /I •i^ X 4 50 LowVt -t 70 "*^"* 90 110 Temperature Figure 2-9. Leakage reduction in 2 NMOS and 2 PMOS stacks at different temperatures and different target threshold voltages, from simulations.

2. Leakage Dependence on Input Vector 25 Hence, the steady state value, K» of the intermediate node voltage can be approximated as, w xy,,+siog~^ V « X a da i + 2A, vv Substituting V^ in either Istack-u or Istack-i will yield the leakage current in a two-stack given by. a f stack =^u ^1~ where a = 1-a h 10 1+2 A , Figure 2-2. Load line analysis showing the leakage reduction in a two-stack. The leakage reduction achievable in a two-stack comprising of transistors with widths Wu and w/compared to a single transistor of width w is given by.

Pp. 69-70, 1999. S. Mutoh et. al, IEEE JSSC, pp. 847-854, Aug. 1995. T. Kuroda et. al, IEEE JSSC, pp. 1770-1779, Nov. 1996. L. Su, R. Schulz, J. Adkisson, K. Beyer, G. Biery, W. Cote, E. Crabbe, D. Edelstein, J. Ellis-Monaghan, E. Eld, D. Foster, R. Gehres, R. Goldblatt, N. Greco, C. Guenther, J. Heidenreich, J. Herman, D. Kiesling, L. Lin, S-H. 25 |im CMOS technology with multiple thresholds and copper interconnects," Intl. Symp. on VLSI Technology, Systems, and Applications, pp. 18-19, 1998.

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